This invention relates to a method of manufacturing a semiconductor device, and more particularly to a manufacturing technique of stabilizing an operation of writing information into each of elements which constitute a mask ROM (Read Only Memory).
In order to shorten the TAT (Turn Around Time) of a mask ROM, various techniques of ion-implanting for writing information (which is also referred to as xe2x80x9cprogram writexe2x80x9d or xe2x80x9cROM writexe2x80x9d) after an Al wiring has been formed are known. Referring to FIGS. 9A to 9D, an explanation will be given of a conventional manufacturing technique.
Step 1: As seen from FIG. 9A, using the technique of thermal oxidation or CVD, a pad oxide film 52 of a silicon oxide film having a thickness of 25 nm is formed on a P-type semiconductor substrate 51. The pad oxide film 52 is formed to protect the surface of the semiconductor substrate 51.
Next, a silicon nitride film 53 which is an oxidation-resistant film is formed on the entire surface. Thereafter, lengthy stripes of openings 53a for forming element isolation films 54 are formed in the silicon nitride film 53 in a direction perpendicular to a paper face of this drawing.
Step 2: As seen from FIG. 9B, using the technique of LOCOS with the silicon nitride film 53 as a mask, the semiconductor substrate 51 is oxidized to form element isolation films 54. At this time, oxide regions invades between the semiconductor substrate 51 and silicon nitride film 53 so that bird""s beaks 54a are formed. Next, the silicon nitride film 53 and pad oxide film 52 are removed, and using the technique of thermal oxidation, a gate insulated film 55 having a thickness of 14 nm to 17 nm is formed. Using the technique of CVD, a poly-Si film having a thickness of 350 nm is formed, and phosphorus is doped to form an N-type conductive film 56.
Step 3: As seen from FIG. 9C, the conductive film 56 is etched in lengthy strips in a direction orthogonal to the element isolation films 54 (it should be noted that the etched region, which is in parallel to the paper face, is not illustrated) to form gate electrodes 56a, which serve as word lines. Using the gate electrodes 56a as a mask, P-type impurities such as boron are ion-implanted to form a source region and a drain region (which are not illustrated since they are formed below both ends of the gate electrode in a direction perpendicular to the paper face).
Through the process described above, memory cell transistors arranged in a matrix shape are formed. An interlayer insulating film 57 having a thickness of 500 nm of a silicon oxide film is formed on the entire surface. Al wirings 58 in lengthy strips, which serve as bit lines, are formed above the element isolation films 54, respectively in a direction perpendicular to the paper face. Until this step, the manufacturing process can be carried out irrespectively of what program should be written in the memory cell transistors. For this reason, the wafers can be previously manufactured. In this case, a silicon oxide film 59 serving as a protection film is formed on the entire surface.
Step 4: At the time when a program to be written is determined on receipt of a request from a customer, as seen from FIG. 9D, a photoresist 60 having openings 60a for writing a program for a mask ROM is formed. P type impurities such as boron are ion-implanted in the semiconductor substrate 51 immediately beneath the gate electrodes 56a by using the photoresist 60 as a mask so that predetermined memory cell transistors are depleted. Thus, the threshold voltages of the memory cell transistors are lowered so that a ROM data is written.
However, generally, the processing accuracy of the photoresist is low, e.g. 0.5 xcexcm. Therefore, the openings 60a formed in the photoresist 60 provide a variation of 0.5 xcexcn. Further, as described above, the element isolation film 54 has the bird""s beak and hence is thinned at its end. Therefore, where there is a variation in the openings 60a, as seen from FIG. 10, as the case may be, implanted impurity ions penetrate the bird""s beak 54a to reach the semiconductor substrate 51 beneath the element isolation film 54, surrounded by circle A. Where such elements are adjacent to each other, a leak current flowing below the element isolation film 54a, as indicated by arrow, occurs between the adjacent elements. This leads to poor element isolation. The improvement of the processing accuracy of the photoresist mask leads to a great increase in cost.
Further, in the semiconductor device incorporating various transistors having different withstand voltages, the thickness of the gate insulated film is set according to the various transistors. For example, where the gate insulated films having two kinds of film thicknesses are to be formed, a thick gate insulated film is once formed on the entire surface, and is etched at the area(s) where a thin gate insulated film is to be formed, and further the thin gate insulated film is formed again.
In this case, when the thick gate insulated film is etched away, the element isolation film will be shaved. During such a process, the thickness of the element isolation film at an ROM part gradually becomes thin.
In the process in which the ROM will be made later, ion-implantation for data write is executed to penetrate an interlayer insulating film, gate electrode and gate insulated film. Therefore, this must be carried out at high energy of 1 MeV to 3 MeV. The ion implantation at such high energy increases the lateral diffusion of implanted ions. This also leads to the poor element isolation as described.
Further, the apparatus for executing ion-implantation at such high energy is generally expensive, which results in an increase in cost.
For the reasons described above, in order to prevent the poor element isolation, the element isolation film must be set in a width larger than a processing limit so as to give sufficient allowance. In addition, it is difficult to thin the element isolation film, which hinders miniaturization. This is a first problem to be solved.
When the interlayer insulating film 57 is etched, the etching does not advance along the edge of the photoresist 60, the sectional shape of the opening is tapered toward the bottom. The ion-implanting in this state leads to inconvenience of poor write due to an etching remainder. This is the second problem to be solved.
In order to solve this problem, where the interlayer insulating film is etched using the photoresist as a mask to form a ROM write region, taking the narrowing of the ion-implanted region due to the tapered portion into consideration, the photoresist is formed so that the diameter of the opening is larger than that of the ion-implanted region.
Thus, the poor ROM write due to the etching remainder of the interlayer insulating film could be avoided.
The above method was suitable for the write for an element at an individual position. However, where the write is done for the regions of adjacent elements, this method gave rise to the following problem.
Specifically, as seen from FIGS. 11A and 11B, in order to carry out the ROM write for the regions where the elements to be written are adjacent, when interlayer insulating films 63, 62, 61 and a part of the interlayer insulating film 57 are etched using as a mask photoresist 64 (which has an opening 64a having a diameter (X2) wider than that (X1) of the ion-implanted region), a thin photoresist remains above the metallic wiring 58 arranged on such a region. Where the interlayer insulating films are etched using the thin photoresist as a mask, as the case may be, the photoresist and interlayer insulating films fall down. This is a cause of a poor product. Incidentally, FIG. 11A is a sectional view taken in line Axe2x80x94A in FIG. 11B showing a semiconductor device in a multi-layer wiring structure.
In view of the first problem described above, in accordance with this invention, the method of manufacturing a semiconductor device including a gate electrode on a semiconductor substrate through a gate insulated film; source/drain regions formed to be adjacent to the gate electrode; and a metallic wiring formed through an interlayer insulating film covering the gate electrode, wherein impurity ions are implanted in a surface layer of the substrate using the metallic wiring and a photoresist formed thereon as a mask, the method has a feature that no photoresist is formed on the metallic wiring arranged above regions in which the impurity ions are implanted in adjacent elements.
Further, the method of manufacturing a semiconductor device has a feature that the metallic wiring is formed in a multiple layer structure, an interlayer insulating film is removed using the photoresist as a mask to expose the metallic wiring at a lowermost layer, and ions are implanted using it as a mask.
Furthermore, the method of manufacturing a semiconductor device has a feature that the impurity ions are implanted to write information in each of elements constituting a mask ROM.
In this way, since the ions are implanted using as a mask the metallic wiring having higher processing accuracy than the photoresist, occurrence of poor element isolation can be inhibited unlike the background art.
Further, where ions are implanted in adjacent elements, no photoresist is formed on the metallic wiring arranged above the corresponding regions. For this reason, the fall-down of the photoresist itself or of both photoresist and its underlying interlayer insulating film in a multi-layer wiring structure due to its being thinned does not occur, which does not cause a poor product.
In view of the second problem, the method of manufacturing a semiconductor device including a gate electrode on a semiconductor substrate through a gate insulated film and source/drain regions formed to be adjacent to the gate electrode, wherein impurity ions are implanted in a surface layer of the substrate using a photoresist as a mask, the method has a feature that the impurity ions are implanted using the photoresist with openings which have different diameters between a region above an element to be ion-implanted and regions above adjacent elements to be ion-implanted.
Further, the method of manufacturing a semiconductor device has a feature that impurity ions are implanted in a surface layer of the substrate using the metallic wiring formed through an interlayer insulating film covering the gate electrode and a photoresist formed thereon as a mask.
Further, the method of manufacturing a semiconductor device has a feature that the metallic wiring is formed in a multiple layer structure, an interlayer insulating film is removed using the photoresist as a mask to expose the metallic wiring at a lowermost layer, and ions are implanted using it as a mask.
Furthermore, the method of manufacturing a semiconductor device has a feature that impurity ions are implanted to write information in each of elements constituting a mask ROM.
In this way, using as a mask the photoresist with openings having diameters corresponding to regions to be ion-implanted, ions are implanted in an element at an individual position or adjacent elements. For this reason, poor write for the element at an individual position is inhibited. In addition, the thinning of the photoresist above the regions where ions are implanted in the adjacent elements is reduced. For this reason, the fall-down of the photoresist itself or of both photoresist and its underlying interlayer insulating film in a multi-layer wiring structure due to its being thinned does not occur, which does not cause a poor product.